Build-Up Film Adhesive in Meeting the Challenges of the Communication and Reliability Challenges

Shear and Z-Axis Tensile Stress Management for Build-Up Substrates

One of the challenges in dielectric film build-up on the BT and Laminate Core are to minimize the shear stress. BT and other core substrate typically have coefficient of thermal expansion (CTE) of 18 ppm/ºC while typical dielectric polymer has CTE around 60 ppm/ºC.   Even with heavy silica filling, the first and even later generations of ABF have typical CTE above 30 ppm/ºC. More deviation from 18ppm/C will induce high shear stress and thus adversely affect the warpage and long-term reliability.

When more layer counts are used in the build-up substrate, the Z-axis expansion fatigue considerations for the copper lined vias an solder joints that have CTE around 18-24ppm/ºC becomes a challenge for the long-term reliability as well.

Build-up substate with organic core substrate must manage the shear stress if there is any substantial CTE differential from the 18ppm/C of the core substrate. Most of the existing ABF solutions have CTE well over 35 ppm/ºC and thus must be capable to handle substantial shear stress induced from cooling from the curing temperature. Along the Z-axis, copper vias interconnection and solder joints with CTE of 18-24 ppm/ºC must also be able to handle the tensile stress during the temperature excursion during the device operation. BUF7880 and BUF7660 are engineered to have CTE of 18-22 ppm/ºC to closely match the copper and core substrate to minimize both the shear and tensile stresses that adversely affect the long-term reliability.
Glass core substrate is being developed to overcome the warpage of the larger area chiplet organic core substrate. In this case, the challenge of CTE mismatch between build-up substate and the glass core substrate with CTE of 3-10ppm/ºC is even more challenging. Build-up film dielectric between 10-18 ppm/C will be more desirable in managing the substantial shear stress induced from cooling from the curing temperature. BUF7883-NP and BUF7889-NP are engineered to have CTE of 8-18 ppm/ºC to closely match the copper and the core substrate to minimize both the shear and tensile stresses that adversely affect the long-term reliability.

Thermal Dissipation Balancing Communication and Stress Management

With the increase use of heterogenous integration, logic and processing chips are directly next to the lesser powered memory modules. More heat generated must be quickly dissipated across and through the build-up substrate. In providing the needy thermal dissipation, AIT with over 30 years of using diamond-based adhesive for supercomputers have developed the diamond filled build-up film dielectric adhesive to provide more than 8 W/mºK thermal dissipation capability. BUF7660 and BUF7880 are filled with nano-based and micron-based diamond crystallites to form BUF7669-NP and BUF7889-FP.

Increasing the thermal dissipation comes also the increase in dielectric constant. Thus, the choice in balance of data communication efficiency must be weighed and balanced with the heat dissipation during the build-up film substrate and packaging considerations.

Build-up substrate for chiplets in the heterogenous packages that include the powerful heat generated GPU, other processors chips, and including HBM that includes the logic chips are generating heat with temperature cumulation to well over 85ºC locally. Traditional build-up films such as ABF typically provide 1-2W/mºK to provide minimal thermal dissipation capability. BUF7889-FP and BUF7669-NP are engineered to bridge this technology gap to appreciably increase the useful life and reliability of these AI based modules.

Low Dielectric Constant and Loss for 5G-6G Devices

In meeting the fast communication speed for 5G and 6G modules, build-up substrates with or without core substrates are preferably with low dielectric constant and loss below 3.0 and 0.005 at the mmWave frequencies. This challenge can only be met with dielectric without the use of inorganic fillers such as silica to control the CTE for stress consideration. Through the use of novel molecularly structural engineering, AIT scientists have successfully created dielectric build-up adhesive film that matches the CTE of copper and BT core substrate at 18-22 ppm/ºC without using highly loaded silica. These high-temperature capable dielectric polymer adhesive films respond to mmWave frequency with low dielectric constant of 2.6-2.8 and less than 0.005 dielectric loss.

BUF7880 and BUF7660 have been specifically engineered with molecular structure to match CTE of copper and core substrate 18-22 ppm/ºC and 2.6-2.8 dielectric constant for mm wave modules and chiplets. The optimization of CTE and dielectric properties provide the stress reduction for reliability while meeting the high-speed communication between processors, HBM and other devices mounted on the build-up substrate.

Coupling High Temperature Stability with High Glass Transition Temperature of >200ºC, and Low CTE of AIT Build-Up Films with 8-22 ppm/ºC Ensures Compatibility with Most Stringent Multilayer on Organic and Glass Core Substrate in Shear and Z-axis expansion stresses

Organic Core Substrate Based Build-Up Substrate Reaching Size Limitation without Low Stress CTE Matching Build-Up Dielectric Film

Organic fiber-glass reinforced core substrate is engineered to have XY-plane CTE to match the copper traces. As long as the build-up dielectric film matches the CTE closely, the overall device will have low shear stress and good reliability. When the chiplet module becomes sizable, the larger size with copper traces vias structure less symmetric, substrate warping may contribute to the shorten longevity of the packaged device.

While the ABF dielectrics in the build-up substrates fabrication were successful, the larger area substrates required for the chiplet packaging is becoming more challenging with the substrate experiencing more warpage and other distortion and stress induced reliability issues. While improving the stress absorption capability with BUF closely matching the organic core substrate and the copper traces may offer relief to the challenge of size and complexity, glass core with inherently flat and better dielectric properties are now in development in earnest to provide better performance and reliability for the next-generation chiplet packaged devices.

AIT BUF7660 and BUF7880 are two of the next generation build-up dielectric film adhesives that offer some options before the glass core substrate development is completed. These novel build-up dielectric adhesives offer the low CTE to of 18-22 ppm/ºC to match that of the organic core and copper traces and vias to minimize the shear and tensile stress and thus minimizing the warpage even for larger area panel-based substrate production.  The following table is an extraction of the key characteristics of the build-up dielectric adhesive that is available for large panel of 600mm with better than 2µm TTV.

The above TSMC format of chiplet packaging is a good example when the CTE of the build-up film dielectric used for build-up substrate on the organic core substrate is closely matching the organic core substrate and the copper traces and vias, the warpage and other stress induced reliability and yield can be minimized.

Glass Core Substrate Benefits Most with New Generation of Build-Up Dielectric Film CTE Closing the Gap of Glass CTE and Copper CTE

Glass core substrate provides many potential benefits if the inherent processing challenges can be met. In the case of build-up dielectric film, traditional ABF may also need to modified to meet the challenge in terms of stress management facing the challenge of glass CTE having CTE from 3-10ppm/ºC depending on the glass composition.

Glass core substrate having CTE of 3-10 ppm/C depending on the glass composition presents a new challenge to have a reliable build-up substrate for chips to be mounted on the fan-up chiplet substrate. Using silica filling volume cannot lower the CTE adequately without too much loss of flow of the BUF to encapsulate the copper traces. AIT BUF build-up film adhesives (BUF7883-NP and BUF7663-SNP) start from the molecular engineering of the polymer matrix before adding the CTE adjusting silica and diamond fillers to achieve the designed CTE of 8-12 while maintaining AIT’s pioneering stress managed polymer matrix.

Copper on Through Glass Via (TGV) May Benefits with a Stress Absorbing Buffer Made of the BUF

The more than 10ppm/ºC in CTE differential between the glass core TGV and the direct plated copper could generate stress-induced cracks on the corners and edges of TGV and copper fatigue cracking of the copper plating.

Direct conformal plating of copper on TGA faces the challenge of CTE mismatch between the glass core and the plated copper.  Extension and shear stresses will affect the reliability and longevity of the device. When conformal plating of copper is on the BUF coated glass core TGV with CTE-matching copper on the TGA faces a similar challenge of CTE-mismatch stresses between the BUF and the glass core. AIT BUF is engineered to absorb the mismatch, the device’s reliability and longevity will improve.

>8 W/m-ºK Thermal Conductivity of AIT Build-Up Film (BUF7669-NP and BUF7889-FP) Coupling with 18 ppm/ºC CTE Ensures Lowering Localized Heating for Longer Device Useful Life and Reliability

With the increase use of heterogenous integration, logic and processing chips are directly next to the lesser powered memory modules. More heat generated must be quickly dissipated across and through the build-up substrate. In providing the needy thermal dissipation, AIT with over 30 years of using diamond-based adhesive for supercomputers have developed the diamond filled build-up film dielectric adhesive to provide more than 8 W/mºK thermal dissipation capability. BUF7660 and BUF7880 are filled with nano-based and micron-based diamond crystallites to form BUF7669-NP and BUF7889-FP.

Increasing the thermal dissipation comes also the increase in dielectric constant. Thus, the choice in balance of data communication efficiency must be weighed and balanced with the heat dissipation during the build-up film substrate and packaging considerations.

Build-up substrate for chiplets in the heterogenous packages that include the powerful heat generated GPU, other processors chips, and including HBM that includes the logic chips are generating heat with temperature cumulation to well over 85ºC locally. Traditional build-up films such as ABF typically provide 1-2W/mºK to provide minimal thermal dissipation capability. BUF7889-FP and BUF7669-NP are engineered to bridge this technology gap to appreciably increase the useful life and reliability of these AI based modules.

Low Dielectric Dk of <2.8 of AIT Build-Up Film Ensures Unparalleled Fast and Non-Distorted Data Communications Between Chips within A Chiplet Mounted on the Substrates

In meeting the fast communication speed for 5G and 6G modules, build-up substrates with or without core substrates are preferably with low dielectric constant and loss below 3.0 and 0.005 at the mmWave frequencies. This challenge can only be met with dielectric without the use of inorganic fillers such as silica to control the CTE for stress consideration. Through the use of novel molecularly structural engineering, AIT scientists have successfully created dielectric build-up adhesive film that matches the CTE of copper and BT core substrate at 18-22 ppm/ºC without using highly loaded silica. These high-temperature capable dielectric polymer adhesive films respond to mmWave frequency with low dielectric constant of 2.6-2.8 and less than 0.005 dielectric loss.

BUF7880 and BUF7660 have been specifically engineered with molecular structure to match CTE of copper and core substrate 18-22 ppm/ºC and 2.6-2.8 dielectric constant for mmWave modules and chiplets. The optimization of CTE and dielectric properties provide the stress reduction for reliability while meeting the high-speed communication between processors, HBM and other devices mounted on the build-up substrate.